September 6-9, 2016
Renaissance Seattle Hotel
Seattle, WA, USA

SOCC 2016 Tutorial Day Program

September 6, 2016

7:30AM – 10:00AM


9:00AM – 10:30AM

Danielle Griffith
Texas Instruments

Design Challenges for the Internet of Things

Gururaj Shamanna
Qualcomm India Pvt Limited

Transistors: Past, Present and Future

10:30AM – 10:45AM

Coffee break

10:45AM – 12:15PM

Malgorzata Chrzanowska-Jeske
Electrical and Computer Engineering Portland State University

3D Integration - Challenges and Advantages


Jacques Christophe Rudell
University of Washington

12:15PM – 2:00PM

Lunch break

2:00PM – 3:30PM

Partha Pande
Washington State University

Bringing Cores Closer Together: The Wireless Revolution in On-Chip Communication

Yong Lian
York University, Canada

The Design Challenges for Self-Powered Wireless Wearable ECG Sensor SoC

3:30PM – 3:45PM

Coffee break

3:45PM – 5:15PM

Visvesh Sathe
University of Washington

Supply Voltage Noise and Mitigation for Real World SoCs

Bhibhudatta Sahoo
University of Illinois, Urbana-Champaign

Vishal Saxena
University of Idaho

ADC Design – From System Architecture to Transistor Level Design

T1A (Room: East)
Design Challenges for the Internet of Things
Danielle Griffith, Texas Instruments

Abstract: The term "the Internet of Things" was first used in 1999 to refer to a network of objects embedded with sensors and wireless connectivity. By 2015, there were 5 billion of these connected devices. Within the next five years, it is predicted that there will be more than 25 billion connected IoT devices. This rapid market growth has been made possible by many innovations in connectivity standards, system architecture, power management, and circuit design. This talk will describe seven different design challenges and the solutions that have been needed for the creation of today's low power, small size, and low cost wireless sensors nodes. These challenges include reducing sleep current, improving power management efficiency, improving the sleep timer frequency stability, reducing start-up time, connectivity standard optimization, reducing active power, and removing external components. The impact of each improvement to the over all system performance will be described, as well as examples of state-of-the-art designs in each of these areas. Further advances that are needed to continue this market growth will also be presented.

GriffithBiography: Danielle Griffith has been with Texas Instruments in Dallas, Texas since 2003 and is a Distinguished Member of the Technical Staff in the Low Power RF group. She develops circuits and techniques for reducing cost, power consumption, and circuit board area for wireless connectivity products that support standards such as Bluetooth Low Energy and Zigbee. Her current focus areas are low power oscillators and MEMS circuitry. She has published 28 papers, 24 of them in IEEE journals or conferences. She has written a book chapter titled "Synchronization Clocks for Ultra-Low Power Wireless Networks" which was published by Springer as a part of the book "Ultra-Low-Power Short-Range Radios". Danielle holds 11 issued US patents and has given multiple university and IEEE conference tutorial and workshop sessions. She was a member of the IEEE RFIC Technical Program Committee for conferences years 2014 and 2015, and has been a member of the IEEE International Solid State Circuits Conference Technical Program committee since conference year 2015. Danielle received the B.S.E.E. and M.Eng. degrees from the Massachusetts Institute of Technology, Cambridge in 1996 and 1997, respectively.


T2A (Room: East)
3D Integration - Challenges and Advantages
Malgorzata Chrzanowska-Jeske, Portland State University

Abstract: The most significant challenge for continued integration of complex systems is energy efficiency. 3D heterogeneous stacking of diverse circuit blocks is one of the most promising solutions. The tutorial will focus on three-dimensional integrated circuits (3D ICs) consisting of multiple layers of systems integrated vertically using through silicon vias (TSVs). We will discuss advantages and challenges of current 3D TSV-based technologies and how to exploit various options through tradeoffs and well-educated choices for designing energy efficient heterogeneous systems. Comparisons between various TSV models and layout solutions will be presented and discussed. Influence of TSV-induced thermo-mechanical stress on devices and interconnects will be discussed. Influence and design trade-offs of temperature distribution on system performance and power dissipation will be discussed. As time permits we will also look towards the horizon, exploring monolithic 3D systems, a variety of new materials such as carbon-nanotubes, and the potential of an abundance of energy efficient interconnects.

MCJeskeColorBiography: Malgorzata Chrzanowska-Jeske is Professor of Electrical and Computer Engineering and Director of the VLSI & Emerging Technology Design Automation Laboratory at Portland State University. From 2004 to 2010 she was Chair of the ECE department at PSU, which she joined in 1989. She holds the Ph.D degree in electrical engineering from Auburn University, Auburn, Alabama. Her research interests include CAD for VLSI ICs, MS-SOCs, 3D ICs, nanotechnology and nano/bio systems, design for manufacturability and design issues in emerging and renewable technologies. She has presented tutorials, keynote and invited talks at various international conferences and events. She has published more than 150 technical papers and serves as a panelist and reviewer for the National Science Foundation (NSF), and as a reviewer for National Research Council Canada (NRC) and many international journals and conferences. Her research has been supported by the NSF and industry. Dr. Chrzanowska-Jeske has served in various roles on the Technical, Steering, and Organizing Committees of many international conferences and workshops, and as Senior Editor, Associate Editor and Guest Editor of international journals. She served for two terms on Board of Governors of IEEE Circuits and Systems Society (CASS). Currently, she serves as Vice President for Technical Activities for the IEEE Nanotechnology Council (NTC). She received the Best Paper Award from Alabama Section of IEEE for the best IEEE Transaction paper in 1990 and IEEE Council on Electronic Design Automation 2008 Donald O. Pederson Best Paper Award in IEEE Transactions on Computer-Aided-Design of Integrated Circuits and Systems.


T3A (Room: East)
Bringing Cores Closer Together: The Wireless Revolution in On-Chip Communication
Partha Pande, Washington State University

Abstract: The continuing progress and integration levels in silicon technologies make complete end-user systems on a single chip possible. This massive level of integration makes modern manycore chips all pervasive in domains ranging from weather forecasting, astronomical data analysis, and biological applications to consumer electronics and smart phones. Network-on-Chips (NoCs) have emerged as communication backbones to enable a high degree of integration in manycore platforms. Despite their advantages, an important performance limitation in traditional NoCs arises from planar metal interconnect-based multi-hop communications, wherein the data transfer between far-apart blocks causes high latency and power consumption. The latency, power consumption, and interconnect routing problems of NoCs can be simultaneously addressed by replacing multi-hop wired paths with high-bandwidth single-hop long-range wireless links. In this talk, we will present design of the millimeter (mm)-wave wireless NoC architectures. We will present detailed performance evaluation and necessary design trade-offs for the small-world network-enabled wireless NoCs with respect to their conventional wireline counterparts in presence of both conventional CMP and emerging big data workloads. We will discuss how Machine Learning can be exploited to design energy efficient Wireless NoC architectures. We will finish this presentation by discussing how the wireless NoC paradigm can enable realization of datacenter-on-chip using heterogeneous processing cores.

Partha PhotoBiography: Partha Pratim Pande is a Professor and holder of the Boeing Centennial Chair in computer engineering at the school of Electrical Engineering and Computer Science, Washington State University, Pullman, USA. His current research interests are novel interconnect architectures for manycore chips, on-chip wireless communication networks, and hardware accelerators for biocomputing. Dr. Pande currently serves as the Editor-in-Chief (EIC) of IEEE Transactions on Multi-Scale Computing Systems (TMSCS) and Associate Editor-in-Chief (A-EIC) of IEEE Design and Test (D&T). He is on the editorial boards of IEEE Transactions on VLSI (TVLSI), ACM Journal of Emerging Technologies in Computing Systems (JETC) and Sustainable Computing: Informatics and Systems (SUSCOM). He was the technical program committee chair of IEEE/ACM Network-on-Chip Symposium 2015. He also serves in the program committee of many reputed international conferences. He has won the NSF CAREER award in 2009. He is the winner of the Anjan Bose outstanding researcher award from the college of engineering, Washington State University in 2013.


T4A (Room: East)
Supply Voltage Noise and Mitigation for Real World SoCs
Visvesh Sathe, University of Washington

Abstract: The past decade has seen a great deal of attention and effort focused on circuits, architectures and methodologies for energy-efficient and low power computing across a broad range of applications from ultra-low power devices to high-end servers. As designers continue to seek and evaluate low power technologies to enable the next generation of computing, the traditionally unheralded problem of voltage margin minimization has emerged to become one of the most significant sources of inefficiency and dissipation. Real-world integrated systems are margined, or guard-banded to address many sources of noise and variability including process, temperature, aging, and supply voltage noise and offsets. The trend toward multiple, fine-grained voltage domains, and aggressively voltage-scaled systems has exacerbated the problem. Voltage-margin minimization is a central component of modern low power design. Indeed, many recent low power efforts in the industry have moved beyond methodology and circuit design to address voltage margin minimization! In this tutorial, I propose a modern treatment of low-power design by actively managing supply-voltage variations. In contrast with text-book approaches, I examine a blend of well-established and emerging solutions that have proven to be effective in real-world constrained systems. The tutorial is organized in two parts. In the first, I begin by analyzing the main contributors toward voltage margins, including practical sources that are related to IC test and product deployment. A subsequent discussion on the major sources of voltage-margins is followed by an examination of a variety of circuit-architecture techniques used to directly and indirectly reduce voltage supply noise margins. High-density de-cap technology, active decap, supply-resonance avoidance, operation-throttling and adaptive clocking techniques to mitigate supply voltage noise. These techniques will be presented in the context of production designs and their constraints for a system-aware treatment of the subject. In the second section, I focus on Integrated Voltage Regulation (IVR) circuits. As designers grapple with more aggressive voltage scaling in the presence of supply variation, Integrated Voltage Regulation (IVR) has emerged as the key to achieving fine spatio-temporal control of SoC supply voltages. IVR has already been deployed for energy-efficient operation in high performance systems (Intel Haswell), and the trend to incorporate IVR to support finer voltage domains continues. We examine recent developments and challenges in the area of integrated voltage regulation across the three major voltage regulator technologies: switching-inductor converters, switched-capacitor converters, and low-dropout (linear) regulators. This tutorial provides an overview of low power circuit and architecture techniques with a system-level context. It is designed to be readily accessible to graduate students and practicing engineers alike, with a blend of well-established and emerging approaches to low power design.

satheBiography:  Dr. Visvesh Sathe received the B.Tech degree from the Indian Institute of Technology Bombay, and the M.S and Ph.D. degrees from the University of Michigan, Ann Arbor. He is currently an Assistant Professor at the University to Washington. Prior to joining the faculty at UW, Dr. Sathe served as a Member of Technical Staff in the Low-Power Advanced Development Group at AMD, where his research focused on inventing and developing new technologies for energy-efficient computing. Dr. Sathe led the research and development effort at AMD that resulted in the first-ever resonant clocked commercial microprocessor. His current research interests include ultra-low power mixed signal circuits for biomedical applications, next-generation clock generation and distribution circuits and architectures, integrated voltage regulation and machine-learning accelerators. Dr. Sathe's research has been invited to top-tier journals. His doctoral thesis was selected as the best dissertation in EECS for 2007 and was nominated for the Rackham Graduate School Distinguished Dissertation Award at the University of Michigan. Several of his inventions in the area of high performance digital design and adaptive clocking for supply noise mitigation have been incorporated in current and future-generation commercial microprocessors. He currently serves as a member of the Technical Program Committees of the Custom Integrated Circuits Conference.


T1B(Room: North)

Transistors: Past, Present and Future
Gururaj Shamanna, Qualcomm India Pvt Limited

Abstract : In this tutorial evolution of transistors from planar technology will be discussed. Scaling limitations of conventional transistors that led to development of Finfet (or 3D) transistors will be presented in detail. Circuit Design challenges associated with 3D transistors will be analysed in this tutorial. Lastly, a brief overview of future transistor architectures beyond Finfet's will be provided.

shamannaBiography: Gururaj Shamanna is a Principal Engineer in Qualcomm India Pvt Limited. He is currently involved in improving the PPA effort for ARM processors that go into Qualcomm developed Snapdragon system-on-chip processors. Prior to joining Qualcomm, Gururaj spent 20 years with Intel Corporation (Hillsboro, Oregon and Bangalore, India) working on generations of Intel microprocessors. Gururaj was awarded Intel Achievement Award (Highest Technical Award in Intel) for his contribution to Intel Xeon Processors. Gururaj has 5 IEEE conference papers and 3 approved patents with 3 more patents pending approval by USPTO. He is a technical reviewer of DAC and a TPC member of SOCC.



T2B (Room: North)
CMOS Integrated System on a Chip for Neural Interface Applications
Jacques (Chris) Rudell, University of Washington

Abstract: The last decade has seen an explosion in research efforts which attempt to miniaturize rack-mounted, neural interface electronics to a form that is easily implantable for in vivo applications. Commensurate with this trend, neural scientist and engineers are demanding higher performance electronics for neural stimulation, recording, encoding, communication and energy harvesting, all in the context of a closed-loop neural interface. Single-chip integration of all the desired electronics appears to be the obvious solution for practical Bidirectional Brain Computer Interfaces (BBCI). However, challenges remain to realize a closed-loop neural interface which must utilize minimal energy, produce high voltages and suppress unwanted spurious signals which are created by “simulation artifacts.” This presentation will start with an overview of integrated neural interface electronics and conclude with a description of some recent work conducted at University of Washington’s Center for Sensorimotor Neural Engineering (CSNE).

lianBiography: Jacques “Chris”tophe Rudell received degrees in electrical engineering from the University of Michigan (BS), and UC Berkeley (MS, PhD). After completing his degrees, he worked for several years as an RF IC designer at Berkana Wireless (now Qualcomm), and Intel Corporation.  In 2009, he moved from industry to academia where he is now an Associate Professor in the department of Electrical Engineering, at the University of Washington. He received the National Science Foundation CAREER award for his work related to mmWave CMOS IC design in 2015.
 While a PhD student at UC Berkeley, Dr. Rudell received the Demetri Angelakos Memorial Achievement Award, a citation given to one student per year by the EECS department. He has twice been co-recipient of the best paper awards at the International Solid-State Circuits Conference, the first of which was the 1998 Jack Kilby Award, followed by the 2001 Lewis Winner Award. He was the co-recipient of the 2008 ISSCC best evening session award, and received best student paper awards from the RFIC Symposium in 2011 and 2014. Dr. Rudell served on the ISSCC technical program committee (2003-2010), and on the MTT-IMS Radio Frequency Integrated Circuits (RFIC) Symposium steering committee (2002-2013), where he was the 2013 General Chair. He was also an Associate Editor for the Journal of Solid-State Circuits (2009-2015).


T3B (Room: North)
The Design Challenges for Self-Powered Wireless Wearable ECG Sensor SoC
Yong Lian, York University, Canada

Abstract: According to the World Health Organization's 2008 report, the top three leading causes of death worldwide are coronary heart disease, cerebrovascular diseases, and lower respiratory infections. Governments and biomedical companies are pouring millions of dollars into research and development to find solutions for these diseases, and technological platforms to support disease management. Wireless biosensors are one such platform, with their ability to measure and communicate parameters that indicate the presence, or onset, of pathology. According to the report from Wearable World, the wearable market for mobile health applications and associated devices will grow at a compound annual growth rate of 61% to reaching $26 billion in revenue by 2017. By any yardstick, this is an explosive trajectory. Yet, the development of wireless biosensors faces huge challenges. So far there are no satisfactory solutions for reliable real-time monitoring of vital signs such as electrocardiogram, blood pressure and, oxygen saturation, not to mention other important parameters such as cardiac output, vessel level flow, glucose, or drug levels to name but a few. This tutorial will cover several topics related to challenges in the design of self-powered wearable wireless biomedical sensor chip including regulatory requirements, skin-electrode interface, design considerations of analog frontend, ADC, signal processing, and wireless transceiver. The focus is on the development of self-powered wearable wireless biomedical sensor SoC, low power techniques and system architecture. Design example, such as self-powered wearable ECG sensor, will be discussed in detail.


lianBiography: Dr. Yong Lian received the B.Sc degree from College of Economics & Management of Shanghai Jiao Tong University in 1984 and the Ph.D degree from the Department of Electrical Engineering of National University of Singapore (NUS) in 1994. He worked in industry for more than 9 years before joining NUS in 1996. He was appointed as the first Provost's Chair Professor in the Department of Electrical and Computer Engineering in 2011. Currently, he is a professor in the Department of Electrical Engineering and Computer Science of York University. His research interests include low power techniques, continuous-time signal processing, biomedical circuits and systems, and computationally efficient signal processing algorithms. He has received more than US$25 million in research funds from various sources. He is the Founder of Clearbridge VitalSigns Pte Ltd, a start-up for commercializing wireless biomedical sensor technologies.

Dr. Lian received more than 20 awards for his research including the 1996 IEEE Circuits and Systems Society's Guillemin-Cauer Award, the 2008 Multimedia Communications Best Paper Award from the IEEE Communications Society, 2011 IES Prestigious Engineering Achievement Award, 2012 Faculty Research Award, 2013 Outstanding Contribution Award from Hua Yuan Association and Tan Kah Kee International Society, 2014 Chen-Ning Yang Award in Science and Technology for New Immigrant, and the latest 2015 Design Contest Award in 20th International Symposium on Low Power Electronics and Design. He is also the recipient of the National University of Singapore Annual Teaching Excellence Awards in 2009 and 2010, respectively.

Dr. Lian is the President-Elect of the IEEE Circuits and Systems (CAS) Society, Steering Committee member of the IEEE Transactions on Biomedical Circuits and Systems. He was the Editor-in-Chief of the IEEE Transactions on Circuits and Systems II for two terms from 2010 to 2013. He served many positions in the IEEE CAS Society including Vice President for Publications, Vice President for Asia Pacific Region, Chair of the Biomedical Circuits and Systems Technical Committee, Chair of DSP Technical Committee, Distinguished Lecturer, etc. He is the founder of several conferences including BioCAS, ICGCS, and PrimeAsia. Dr. Lian is a Fellow of IEEE and Fellow of Academy of Engineering Singapore.


T4B (Room: North)
ADC Design – From System Architecture to Transistor Level Design
Bhibhudatta Sahoo, University of Illinois, Urbana-Champaign
Vishal Saxena, University of Idaho

 AbstractPipelined and Delta-Sigma (ΔΣ) ADCs are increasingly becoming popular in mixed-signal system-on-chip (SoCs). This tutorial combines theoretical as well as practical perspectives on ADC design with special focus on two types of ADCs, viz., CT-ΔΣ ADC and pipelined ADC. The goal is to provide a complete picture to the audience, starting from system level architecture to their transistor-level design. The tutorial will cover basics of ΔΣ modulation, both continuous-time (CT) as well as discrete-time, and pipelined ADCs. System-level behavioral modeling using Matlab/Simulink environment will be presented. The top-down design approach will discuss circuit implementation and include circuit non-idealities in the behavioral modeling. Case studies will be presented for CT ΔΣ ADCs and various digital calibration techniques for pipelined ADCs.

ΔΣ ADCs can be implemented either using discrete-time (switched-capacitor) loop-filter or a continuous-time loop filter. These two implementations have their own advantages and disadvantages. While discrete-time (DT) ΔΣ ADCs are well understood and popular in industrial designs, continuous-time (CT) ΔΣ ADCs have gained a considerable amount of interest in the academic community, followed by early industrial adoption. CT-ΔΣ ADCs are becoming an attractive architecture in broadband wireless communication systems due to several desirable features including inherent anti-aliasing filtering (AAF), relaxed bandwidth requirements of the active elements and much lower power consumption. However, there are few challenges in the widespread adoption of CT-ΔΣ ADCs in industrial designs due to the design complexity resulting from a hybrid CT and DT system, and sensitivity to clock jitter and RC time constant variation.

Pipelined analog-to-digital converters are commonly used for applications that require high-speed and resolutions of approximately 8-14 bits. They present significant advantages compared to high-speed flash ADCs, that require large number of comparators, and high-resolution successive approximation ADCs, that require large number of clock cycles. Since, switched capacitor circuits are the primary building blocks of pipelined ADCs, the accuracy and linearity of pipelined ADC is limited due to capacitor mismatch, finite op amp gain, and op amp nonlinearity. Various methods like trimming, error averaging, etc. have been used in early days to address the accuracy and linearity limitations in pipelined ADCs. These techniques can be categorized as analog calibration techniques. Aggressive device scaling, resulting in high-speed and low-power digital circuits, have led to the adoption of digital calibration techniques to realize high-speed, low-power, and high-resolution pipelined ADCs.

saxenaBiography:  Vishal Saxena is an Associate Professor and Micron Endowed Chair in the Electrical and Computer Engineering Department at the University of Idaho. Previously, he was an Assistant and then Associate Professor at Boise State University from 2010 to Spring 2016. He graduated with a Ph.D. from Boise State University, ID in 2010. He obtained his B. Tech. degree in Electrical Engineering from Indian Institute of Technology, Madras in 2002. In between, he has held senior design position in broadband communication system design in a start-up, circuit design positions in Micron Imaging group (later Aptina) in Boise, ID and Lightwire Inc. in Allentown, PA. At UoI, he directs the Analog Mixed-Signal and Photonic Integrated Circuits (AMPIC) Lab and teaches courses on Mixed-Signal IC design. Dr. Saxena received the prestigious 2015 NSF CAREER, and 2016 AFOSR Young Investigator Program (YIP) awards. He is a member of IEEE and has been an Associate Editor for IEEE TCAS-II journal from 2013-2015. He currently serves on the steering committee of IEEE MWSCAS conference and was the local arrangement chair and Track chair for Analog and Mixed-Signal circuits for the MWSCAS 2012. His research interests include Delta-Sigma data converters, CMOS photonic interconnects, RF photonics, and Neuromorphic circuits and systems. Dr. Saxena has taught a tutorial on Delta-Sigma ADCs at the MWSCAS 2012 in Boise. Also, he has previously taught a widely popular semester long graduate course on Delta-Sigma Data Converter Design.

sahooBiography:  Bibhudatta Sahoo received the B. Tech. degree in Electrical Engineering from Indian Institute of Technology, Kharagpur, India, in 1998, the MSEE degree from University of Minnesota, Minneapolis, in 2000, and PhDEE degree from University of California, Los Angeles, in 2009. From 2000 to 2006, he was with DSP Microelectronics Group at Broadcom Corporation, Irvine, CA, where he designed analog and digital integrated circuits for signal processing applications. From December 2008 to February 2010, he was with Maxlinear Inc., Carlsbad, CA, where he was involved in designing integrated circuits for CMOS TV tuners. From March 2010 to November 2010 he was a Post Doctoral Researcher at University of California, Los Angeles. From December 2010 to December 2011 he was Assistant Professor in the Department of Electronics and Electrical Communication Engineering at Indian Institute of Technology, Kharagpur, India. From December 2011 to December 2015 he was Associate Professor in the Department of Electronics and Communication Engineering at Amrita University, Amritapuri, India. Since January 2016 he has been a Research Scientist at University of Illinois, Urbana-Champaign, IL, USA. His research interests include data converters, signal processing, and analog circuit design. He received the 2008 Analog Devices Outstanding Student Designer Award. He is currently the Associate Editor of IEEE Transactions on Circuits and Systems-II.

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